The present invention relates to the field of programmable devices, and systems and methods for programming the same. Programmable devices, such as field programmable gate arrays (FPGAs), typically include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform logic operations. Programmable devices typically also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more embedded memory array blocks. The logic cells and functional blocks typically are interconnected with a configurable switching circuit, which selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
Programmable devices typically include one or more input/output (I/O) banks for communication with external devices, such as memory devices, network interfaces, data buses and data bus controllers, microprocessors, other programmable devices, application-specific integrated circuits (ASICs), or virtually any other type of electronic device. Each I/O bank is connected with a number of conductive I/O pins, balls, or other electrical connectors in the programmable device chip package. An I/O bank includes logic for sending and receiving data signals, control signals, clock signals, power and ground signals, or any other type of signal used in conjunction with communications between the programmable device and an external device.
The I/O banks of a programmable device typically include logic, amplifiers, filters, and other circuits that together can be configured to provide one or more standard interfaces between the programmable device and external devices. Additionally, the I/O banks of a programmable device can be configured to provide custom or proprietary interfaces if required by a particular application.
Simultaneous switching noise (SSN) is one of the many challenges facing the design and implementation of high speed external interfaces. These interfaces typically involve a large number of pins switching at substantially the same point in time. For example, a DDR-II 72-bit interface between an FPGA and external memory devices can have 72 simultaneously switching bits, which can cause signals such as a ground signal or supply voltage (e.g., Vcc) signal to bounce or sag. If the magnitude of the noise is large enough and/or the duration long enough, the noise can adversely affect the functionality of the programmable device and overall system due to poor signal integrity. This noise problem also generally increases with higher performance requirements.
A prior approach to reducing SSN is to optimize the circuit board supporting the system of programmable devices and/or other devices. For example, designers can use 20 layer circuit boards instead of 10 layer circuit boards to allow for additional ground planes. The additional ground planes help minimize sags or bounces in the various signals, thereby reducing the amount of SSN in the system. This solution is not optimal, however, as the overall cost, manufacture time, and/or complexity of the systems can be substantially increased.